1. Field of the Invention
The present invention relates generally to a received signal strength indicator (RSSI) circuit, and more particularly, to a high-speed digital RSSI circuit which is capable of performing auto gain control (AGC), independently of a baseband signal processor modem, and capable of detecting the strength of a received signal at a high speed without using an external capacitor.
2. Discussion of the Related Art
Information or image signal broadcasts through air are usually transmitted at a high frequency such as frequency (RF). The RF signal is received through an antenna of a receiver. The received signal is converted into a signal of an intermediate frequency (IF) or a baseband via a low noise amplifier (LNA) and a down conversion mixer. Then, interfering signal components of the converted signal are removed using a band pass filter or a low pass filter such that only desired signal components are transmitted to an IF signal processor or a baseband signal processor. The LNA, a mixer, and an integrated filter circuit have limited dynamic range, and thus, it is necessary to control their gain and linearity according to the strength of a received signal.
The physical layer of wireless communication systems, such as code-division multiple access (CDMA) systems, global systems for mobile communication (GSM), and wireless local area networks (WLAN) etc., processes an analog baseband signal. Then, in another layer, a baseband modem converts the analog signal to digital signal and performs digital modulation and an operation according to a digital RSSI to feed back information for automatic gain control. In less elaborate systems, such as one using bluetooth technology, the modulation or RSSI operations are performed in the physical layer. In such systems, automatic gain control is performed without the baseband modem, and such gain control must be performed at high speed so that receipt of input signal is not interrupted.
FIG. 1 is a block diagram of a conventional RSSI.
Referring to FIG. 1, the phase difference between I-Path and Q-Path is 90° Fullwave rectifiers 80 and 90 generate current by fullwave rectifying an output signal for each end of multi-stage amplifiers, e.g., limiters 60 and 70, and the generated current is summed up by an adder 100. The summed up current is converted into a voltage by an RC parallel load 120. An A/D converter 110 converts the voltage signal to a digital signal based on a reference voltage Vref and outputs the digital signal as a digital RSSI code. Gains of low noise amplifier LNA 10 and mixers 20 and 30 are controlled by the digital RSSI code.
The capacitor C of the RC parallel load 120, which is used to smooth-over ripples occurring when the output signal is fullwave-rectified, is usually placed outside an integrated circuit, and a large capacitor is required. However, as the capacitance of the capacitor C increases, the time required to charge up the capacitor increased, and thus, a RSSI response time, e.g., the time required to generate the digital RSSI code and control the gains of the LNA 10 and the mixers 20 and 30 according to the generated RSSI code, is also increased. In other words, there is a trade off between an increase in the capacitance of the capacitor C and an increase in the RSSI response time.
FIGS. 2A through 2D illustrate graphs of digital RSSI data generated when a time division duplex (TDD) communication system receives a signal.
As shown in FIG. 2A, the TDD communication system, where the frequency of a received signal is the same as that of a transmitted signal, divides one frame into a channel for transmitting and a channel for receiving to enable two-way communication with one channel frequency.
FIG. 2B shows an enlarged view of one pulse of the received signal of FIG. 2A and FIG. 2C is a graph of the received signal of FIG. 2B converted into a voltage signal by the RC parallel load 120. Referring to FIG. 2C, the delay in converting an input signal RXIN into a voltage signal increases in proportion to the time required for the capacitor C of the RC parallel load 120 to charge.
FIG. 2D shows the voltage signal which is shown in FIG. 2C converted into digital RSSI data by the A/D converter 110. Referring to FIG. 2D, a delay in generating the digital RSSI data increases in proportion to the sampling time required for digital conversion in the A/D converter 110.
When the digital RSSI data are generated by using the RC parallel load 120 and the A/D converter 110, the delay in generating the digital RSSI data occurs in proportion to the time required for the capacitor C of the RC parallel load 120 to charge and the sampling time required for digital conversion in the A/D converter 110. Accordingly, the time required for controlling the gains of the LNA 10 and the mixers 20 and 30 according to the digital RSSI data is expected to be prolonged.
In addition, the A/D converter 110 requires a reference voltage Vref in converting the inputted signal into a digital signal. It can be seen that the accuracy of the Vref significantly affects accuracy of the digital RSSI data. Therefore, an accurate reference voltage Vref is needed to provide accurate RSSI date. However, as in known in the art, different Vrefs can result due to variations in changes due to manufacturing processes. As a result, the accuracy of the digital RSSI data will likewise vary.
FIG. 3 is a graph showing characteristics of RSSI data outputted from the system of FIG. 1.
Referring to FIG. 3, when the strength of the received signal is small, the gain of the mixer 20 is controlled by the RSSI data. When the strength of the received signal is large, the gain of the LNA 10 is controlled by the RSSI data to control the strength of the received signal. Here, when the gain of the LNA or the mixers is changed from a low level to a high level or from a high level to a low level, appropriate hysterisis is needed to remove instability.